Open Access
Table 4
Details of encoder and decoder architecture for 96 × 96 pixel inputs.
| Encoder layers | Decoder layers | ||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|
| Layer | In Ch. | Out Ch. | Kernel | Stride | Padding | Layer | In Ch. | Out Ch. | Kernel | Stride | Padding |
| PCDown1 | 1 | 32 | 3 | 1 | 1 | PCUp1 | 512 | 512 | 3 | 1 | 0 |
| PCDown2 | 32 | 64 | 4 | 2 | 1 | PCUp2 | 1024 | 512 | 4 | 2 | 1 |
| PCDown3 | 64 | 64 | 3 | 1 | 1 | PCUp3 | 1024 | 512 | 3 | 1 | 1 |
| PCDown4 | 64 | 128 | 4 | 2 | 1 | PCUp4 | 1024 | 256 | 4 | 2 | 1 |
| PCDown5 | 128 | 128 | 3 | 1 | 1 | PCUp5 | 512 | 256 | 3 | 1 | 1 |
| PCDown6 | 128 | 256 | 4 | 2 | 1 | PCUp6 | 512 | 128 | 4 | 2 | 1 |
| PCDown7 | 256 | 256 | 3 | 1 | 1 | PCUp7 | 256 | 128 | 3 | 1 | 1 |
| PCDown8 | 256 | 512 | 4 | 2 | 1 | PCUp8 | 256 | 64 | 4 | 2 | 1 |
| PCDown9 | 512 | 512 | 3 | 1 | 1 | PCUp9 | 128 | 64 | 3 | 1 | 1 |
| PCDown10 | 512 | 512 | 4 | 2 | 1 | PCUp10 | 128 | 32 | 4 | 2 | 1 |
| PCDown11 | 512 | 512 | 3 | 1 | 0 | PCUp11 | 64 | 1 | 3 | 1 | 1 |
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